Workpackage 1

 Title

Graphene as intermediate electrode (Leader: Dr Ilia Valov)

Duration

Τ0 – Τ0+24

Description

In this workpackage, FZJ will delivere Si/SiO2 substrates with bottom electrodes to NCSRD for graphene layers transfer. Graphene substrates will be provided to the project by AIXTRON. Next the wafers will be sent back to FZJ for the solid-state electrolyte material deposition and return to NCSRD to deposit the top graphene layers. The final top electrode will be deposited at FZJ by sputtering. The patterning of the top electrode will be done photolithography at FZJ. It should be emphasized that after top electode patterning G-layers should be patterned too by O2 plasma with top electrodes acting as hard mask. Such a fabrication step could be done at NCSRD. ECM and VCM devices will be realized and tested.

WP1 Deliverables

D.No.

Title

Description

D1.1

Report on fabrication of ECM ReRAM cells with G as intermediate electrode

Report and detail description of the fabrication recipes of the new ECM ReRAM cells with G as intermediate electrode

D1.2

Report on fabrication of VCM ReRAM cells with G as intermediate electrode

Report and detail description of the fabrication recipes of the new VCM ReRAM cells with G as intermediate electrode

 

 

Workpackage 2

 Title

Graphene as active electrode (Leader: Dr Ilia Valov)

Duration

Τ0 – Τ0+24

Description

In this workpackage, FZJ will delivere Si/SiO2 substrates without bottom electrodes to NCSRD for graphene layers transfer (counter electrode). Graphene substrates will be provided to the project by AIXTRON. Next the wafers will be sent back to FZJ for the solid-state electrolyte material deposition and return to NCSRD to deposit the top graphene layers. The final top electrode will be deposited at FZJ by sputtering. The patterning of the top electrode will be done photolithography at FZJ. It should be emphasized that after top electode patterning G-layers should be patterned too by O2 plasma with top electrodes acting as hard mask. Such a fabrication step could be done at NCSRD. ECM and VCM devices will be realized and tested.

 

WP Deliverables

D.No.

Title

Description

D2.1

Report on fabrication of ECM ReRAM cells with G as counter electrode

Report and detail description of the fabrication recipes of the new ECM ReRAM cells with G as counter electrode

D2.2

Report on fabrication of VCM ReRAM cells with G as counter electrode

Report and detail description of the fabrication recipes of the new VCM ReRAM cells with G as counter electrode

 

 

Workpackage 3

 Title

Novel development of Graphene layers (Leader: Dr Panagiotis Dimitrakis)

Duration

Τ0 – Τ0+24

Description

Ion implantation of Si, P, B and N will be carried out in SiC substrates and subsequently annealed at temperatures below 1100 °C in order to form graphene layers. Due to the creation of large amount of dangling bonds between Si and C in SiC substrates created by ion implantation and the energy favorable chemical binding of Si with the implanted atoms, carbon atoms are moving to the surface of the substrate under thermal annealing where they are binding together forming graphene. This approach will be followed by NCSRD in the workpackage to realize G-monolayers at temperatures lower than 1100 °C. Furthermore, these layers will be used as active electrodes to test ReRAM devices with HfOx and or TaOx deposited by ALD. In the later devices, G-layers will not suffer from defects, chemical residuals, cracks as well as ion contamination.

WP Deliverables

D.No.

Title

Description

D3.1

Report on G-formation by Si implantation in SiC

Report will contain a detailed description of the ion implantation and annealing conditions as well as results from Raman spectroscopy revealing the formation and the quality the G-layers on SiC substrate.

D3.2

Report on G-formation by P, As, B, N implantation in SiC

Report will contain a detailed description of the ion implantation and annealing conditions as well as results from Raman spectroscopy revealing the formation and the quality the G-layers on SiC substrate.

D3.3

Report on G-formation by P, As, B and N co-implantation of Si in SiC

Report will contain a detailed description of the ion implantation and annealing conditions as well as results from Raman spectroscopy revealing the formation and the quality the G-layers on SiC substrate.

D3.4

Report on the ReRAM device fabricated using the novel synthesised G-layers on SiC

Report on the fabrication and electrical characterization of novel VCM cells on SiC substrates with graphene as active layer.

D3.5

Midterm report

Midterm report and success milestones

 

 

Workpackage 4

 Title

Structure and Device characterization (Leader: Ilia Valov)

Duration

Τ0 – Τ0+24

Description

Structural characterization (XRD, XRR, Raman) and surface morphology characterization (AFM, HRSEM) are necessary to control the quality of the proposed structures before device fabrication. SIMS and XPS will be used to investigate the in-depth distribution of elements in the layered structure and their chemical state, respectively. The stability of the chemical state of the graphene layer will be checked by XPS. SIMS depth profiling will be used to monitor the effect of graphene layer as diffusion barrier. The influence of the electrical and thermal (up to 120 °C) stress on these parameters will be examined. All these characterization techniques will be employed by FZJ.

AC and DC techniques will be used for electrical characterization of the fabricated devices to determine the effect of the insertion of graphene layers on the device impedance. The resistive switching will be first qualitatively tested by current-voltage (I-V) sweeps. The main electrical characterization in respect to the switching kinetics, endurance and retention will be performed by pulse measurements. The effect of the temperature on the electrical characteristics of the devices will be studied in the range 20 °C to 120 °C. The tests will be performed on own developed measurement stations fully computerized and capable of automatically recognition of patterned structures. This will allow a large number of devices to be tested ensuring statistical verification of the results. These will be employed by FZJ. In addition, the fabricated devices will be additionally characterized by cAFM and STM at NCSRD. Due to the large number of samples, NCSRD will undertake temperature variable measurements (I-V, data retention, etc) on selected devices from WP1 and WP2. Furthemore, NCSRD will carry out the electrical characterization of VCM devices fabricated by ALD as well as the electrical characterization of 30nm crossbar memory cells. The research team at NCSRD has developed in the past various measurement protocols for NVMs. It should be emphasized that the electrical characterization laboratory at NCSRD is ISO 9001:2008 and 17025 certified.

 

WP Deliverables

D.No.

Title

Description

D4.1

Structural characterization of ECM and VCM cells

Report on the structural properties of the memory stacks including XRD and XRR, SIMS and XPS measurements including HRSEM studies, surface analysis by AFM measurements and Raman spectroscopy measurements to characterize the transferred G-layers.

D4.2

Electrical characterization of ECM and VCM ReRAM cells with G as intermediate electrode

Report on the results of electrical characterization including memory performance measurements (W/E speed, Endurance and data retention).

D4.3

Electrical characterization of ECM and VCM ReRAM cells with G as active electrode

Report on the results of electrical characterization including memory performance measurements (W/E speed, Endurance and data retention).

D4.4

Report on AFM, cAFM and STM strudies of ReRAM cells

Report on the electrical characterization results employing scanning probe microscopy techniques

D4.5

Electrical characterization of <30nm ReRAM cells

Report on the electrical characterization results from nano-crossbar memory cells.

 

 

Workpackage 5

 Title

Downscaling of ReRAM cells below 30nm (Leader: Dr Panagiotis Dimitrakis)

Duration

Τ0+12 – Τ0+24

Description

Selected structures provided by WP1, WP2 and WP3 that exhibited outstanding performance will be integrated below 30nm using the state-of-the-art EBL tool provided by NCSRD. The crossbar architecture will be followed. The formation of the top metal electrode at <30nm is a major issue and we will handle this by exploring different metal deposition techniques (thermal evaporation, sputtering, ALD) and patterning methods such as lift-off or metal plasma etching. Another issue that is challenging is the dry anisotropic etching of the memory stack. It should be noticed here that the line edge roughness of the top metal electrode is of critical importance ans should be minimized. Otherwise, the metal edge roughness will be transferred to the sidewalls of the memory stack. Measurement of the line edge roughness will be carried out by software analysis of SEM images. The software is developed at NCSRD.

 

WP Deliverables

D.No.

Title

Description

D5.1

Report on fabrication of <30nm ReRAM cells

Detail description and optimization of the fabrication process (e-beam lithography process, RIE conditions and plasma chemistry) including SEM images and analysis.

D5.2

Workshop Organization report

Report on the outcome of the Workshop

D5.3

Final report

Final report and main achievements

 

 

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